Coordinating the operation of the computer system's memory hardware resources is a primary task of an operating system. An operating system, in conjunction with the dedicated memory management hardware of the computer system, manages the computer system's memory resources through the use of memory management protocols. The memory management protocols are necessary to maintain "coherency" between data existing simultaneously in different locations (e.g., a block of instructions stored in both main memory and an instruction or data cache). Coherency refers to the consistency of the data stored in two or more locations. A cache which is consistent with main memory is referred to as a coherent cache. The process of making a cache coherent is referred to as cache synchronization.
A central processing unit (cpu) speeds memory accesses by accessing "cache resident" instructions or data whenever possible. A "cache hit" is where the next instruction or data of a software process resides in the cache, in addition to main memory. An instruction cache is a specialized cache which provides fast temporary storage of software instructions. When the next instruction of a software process resides in the instruction cache, the instruction is quickly fetched and executed, as opposed to accessing main memory. Where the instructions in the instruction cache are not consistent with main memory (e.g., incoherent), a program can process inaccurate data or can execute improper instructions.
Maintaining instruction cache coherency is a particular problem with regard to software emulation programs. More particularly, instruction cache coherency is a problem for software emulation programs where the program code of a non-native software program is both translated into native program code and executed on the computer system at run time (e.g., on the fly). Because instructions are continually being written to main memory and executed, instruction cache incoherency occurs more frequently with software emulation programs than with other types of programs.
A first solution to the above problem is to fabricate a cpu having hardware cache synchronization circuitry. In such a cpu, instruction cache coherency is maintained by dedicated hardware, e.g., the Power PC 601 from Motorola corporation. The use of dedicated hardware cache synchronization circuitry eliminates the need for memory management protocols, since instruction cache coherency is maintained automatically. Dedicated hardware synchronization circuitry, however, can be an expensive and complex solution and may slow down the processor by increasing the minimum cycle time.
A second solution to the above problem is to fabricate a cpu having a native instruction where the native instruction accomplishes instruction cache synchronization. In such a cpu, a native instruction cache synchronization instruction is simply part of that cpu's instruction set. The cpu architecture, however, must be designed from the outset to support a native instruction cache synchronization instruction (e.g., RISC cpu architectures, where instructions are implemented in hardware rather than micro-code).
A third solution to the above problem is to implement an instruction cache synchronization instruction through a call to the operating system. A program running on the computer system manipulates the instruction cache by executing a "call" to the operating system. The operating system then steps through its memory management protocols and carries out the instruction cache synchronization. Instruction cache synchronization, however, takes a relatively long time to execute via an operating system call. The operating system steps through its memory management protocols and carries out the desired request if it determines it is "safe" to do so. This ensures the computer system runs reliably, especially when there are other software processes executing simultaneously on the system and also relying on the instruction cache.
Thus, what is desired is a method of initiating instruction cache synchronization instructions directly from user mode without the "overhead" associated with an operating system call. What is desired is a method and system of initiating an instruction cache synchronization instruction directly from user mode in a fast and efficient manner. What is further desired is a method of initiating instruction cache synchronization instructions without requiring dedicated and complex hardware to support the instruction. What is further desired is a method of executing an instruction cache synchronization instruction in a cpu architecture which does not specifically support a native instruction cache synchronization instruction in user mode. The present invention provides the above advantageous features.